Grid-voltage Synchronization Algorithms Based on Phase-locked Loop and Frequency-locked Loop for Power Converters

dc.contributorAalto-yliopistofi
dc.contributorAalto Universityen
dc.contributor.authorFuad, Khaled
dc.contributor.schoolSähkötekniikan korkeakoulufi
dc.contributor.supervisorHinkkanen, Marko
dc.date.accessioned2014-06-26T09:34:35Z
dc.date.available2014-06-26T09:34:35Z
dc.date.issued2014-06-16
dc.description.abstractThe purpose of this thesis is to study and find the appropriate grid-voltage synchronization method for grid-connected converters under different kinds of faults like phase unbalancing, harmonics, offset and voltage sags. The main purpose of grid-synchronization algorithms is to estimate the positive- and negative-sequence components of the utility voltage under unbalanced and distorted condition. The existing most advanced phase-locked loop (PLL) and frequency-locked loop (FLL) methods are well known method for grid-synchronization. The fundamental variable estimated by the PLL is the grid-phase angle, whereas the grid frequency is the one for the FLL. The most extended technique used for grid synchronization in three-phase three wire system is a synchronous reference frame PLL (SRF-PLL). The SRF-PLL works accurately during balanced condition, but cannot estimate voltage components during unbalanced condition. The Decoupled Double Synchronous Reference Frame PLL (DDSRF-PLL) is might be a substantiation solution for the estimation of the sequence components of the utility voltage under unbalanced condition. Another method based on the FLL, a double second-order generalized integrator FLL (DSOGI-FLL) has also the ability to detect the positive- and negative-sequence components of the utility voltage under unbalanced condition. DDSRF-PLL and DSOGI-FLL algorithms are tested under different kinds of faults and compared with each other. The results show that their performance under harmonic-distorted condition is not really acceptable. A new algorithm based on SRF-PLL, decoupled multiple synchronous reference frame PLL (DMSRF-PLL) might be a better solution for accurate detection of the positive- and negative-sequence voltage components under unbalanced and harmonic distortion condition.en
dc.format.extent45+10
dc.format.mimetypeapplication/pdf
dc.identifier.urihttps://aaltodoc.aalto.fi/handle/123456789/13585
dc.identifier.urnURN:NBN:fi:aalto-201406272262
dc.language.isoenen
dc.locationP1fi
dc.programmeEST - Master’s Programme in Electrical Engineeringfi
dc.programme.majorElectrical Drivesfi
dc.programme.mcodeS3016fi
dc.rights.accesslevelopenAccess
dc.subject.keyworddecoupling networken
dc.subject.keywordfrequency-locked loopen
dc.subject.keywordgrid-connected converteren
dc.subject.keywordphase-locked loopen
dc.subject.keywordsecond order generalized integrator.en
dc.titleGrid-voltage Synchronization Algorithms Based on Phase-locked Loop and Frequency-locked Loop for Power Convertersen
dc.typeG2 Pro gradu, diplomityöen
dc.type.okmG2 Pro gradu, diplomityö
dc.type.ontasotDiplomityöfi
dc.type.ontasotMaster's thesisen
dc.type.publicationmasterThesis
local.aalto.digifolderAalto_05995
local.aalto.idinssi49398
local.aalto.openaccessyes
Files
Original bundle
Now showing 1 - 1 of 1
No Thumbnail Available
Name:
master_Fuad_Khaled_2014.pdf
Size:
1.59 MB
Format:
Adobe Portable Document Format
Description: