Multi-output Synthesizers for Integrated Transceivers

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School of Electrical Engineering | Doctoral thesis (article-based) | Defence date: 2022-03-11
Degree programme
120 + app. 88
Aalto University publication series DOCTORAL THESES, 27/2022
This thesis focuses on concepts, designs and implementations of various multi-output clocking circuits for RF front-ends in mobile terminals. A total of three experimental concepts and five evaluation designs are discussed. Two in-situ calibration concepts are shown to equalize the latencies between plural outputs in stretched multi-output arrangements. Both calibration techniques demonstrated that a digital engine can be run directly from multiple outputs while calibrating their latencies and locking the chained stages delay to the reference cycle. A third side concept of over-an-octave frequency source is presented in the form of a switched-oscillator stacked within a distributed multiplexing network for which the simulations supported the frequency coverage of the stacked oscillators. Two evaluation designs of multi-output code-to-time converters are presented in distinct implementations that eliminate the bulky arrays of passive components. The first embodiment uses active delay cells in branched chains to generate driving waveforms for a quadratures mixer in the receiver and demonstrates LO-phase shifting sufficient for practical beamsteering applications. The second all-digital embodiment with a theoretically unbounded number of delaying channels and a shared communication bus demonstrates a delay tuning range wide enough for sub-6GHz phase modulators. The third prototype design in this work is an all-digital inductor-less PLL driving the frequency multiplier. It is shown by the presented implementation that a PLL-controled ring oscillator can generate multiple phase shifted signals for the inputs of the frequency multiplier. The discussed arrangement exploits a small area and the wide tunability benefits of a sub-6GHz ring oscillator and uses programmable multiplication to translate PLL output frequency into several Gb/s data-rates, thus reducing exclusive pins for an application processor in the limited mobile space. The fourth evaluation design discussed in the thesis is delay-line based multiplier for fractional-N multiplication of the reference frequency. It is verified in the presented work that large frequency jumps can be achieved without compromising the resolution of the channel selection, which makes it possible to rapidly search for unoccupied spectrum in sub-6GHz front-ends. Furthermore, the output quantization noise after frequency multiplication can be shaped with a delta-sigma modulator and output deterministic jitter can be significantly reduced with a post-modulator. The fifth implementation presented in this work is a synthesizer of the pulse streams for multiple mixers in paralleled receiving front-ends. The thesis demonstrates that the generation of pulses can be split into waveform generation and further processing of the waveform, which supports on-chip scalability both in the number of driven mixers and output phases. Furthermore, since pulses are separately generated  close to mixers, there is no need for a synthesizer-centered layout.
Supervising professor
Ryynänen, Jussi, Prof., Aalto University, Department of Electronics and Nanoengineering, Finland
Thesis advisor
Stadius, Kari, Dr., Aalto University, Finland
CMOS, delay line, delay-locked loop, integrated circuit design, 5G mobile communication, digital-to-time conversion, beam steering, on-chip calibration, digital control, oscillator
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