Increasing Fault Tolerance in MPI Stencil-Based Simulations

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Zabelin_Timofey_2025.pdf (469.86 KB)

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Insinööritieteiden korkeakoulu | Bachelor's thesis
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Date

2025-05-09

Department

Major/Subject

Computational Engineering

Mcode

ENG3045

Degree programme

Aalto Bachelor’s Programme in Science and Technology

Language

en

Pages

20+7

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Abstract

This thesis investigates fault-tolerance strategies in a high-performance computing environment focusing on their applicability in stencil-based applications. The strategies are demonstrated with a model application simulating heat propagation. Through a literature review it was discovered that approaches that rely on checkpointing are applicable for stencil-based applications. After mathematical modelling and empirical measurements, it was found that diskless checkpointing does not provide a significant advantage in this scenario over checkpointing with disk due to relatively small checkpoint size. Furthermore, the developed mathematical model, which predicts the expected running time for a given fault tolerance technique, can be utilized to assess the applicability of these techniques in scenarios beyond the scope of this thesis.

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Supervisor

St-Pierre, Luc

Thesis advisor

Puro, Touko

Keywords

fault tolerance, stencil-based algorithms, high-performance computing, mpi

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https://urn.fi/URN:NBN:fi:aalto-202507015506

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[kand] Insinööritieteiden korkeakoulu / ENG