A Self-Calibrated Activation Neuron Topology for Efficient Resistive-Based In-Memory Computing

2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023, IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC

Abstract

In-Memory Computing (IMC) accelerators based on resistive crossbars are emerging as a promising pathway toward improved energy efficiency in artificial neural networks. While significant research efforts are directed toward designing advanced resistive memory devices, the nonidealities associated with practical device implementation are often overlooked. Existing solutions typically compensate for these nonidealities during off-chip training, introducing additional complexities and failing to account for random errors such as noise, device failures, and cycle-to-cycle variability. To tackle this challenge, this work proposes a self-calibrated activation neuron topology that offers a fully online non-linearity compensation for IMC accelerators. The neuron merges multiply-accumulate operations with Rectified Linear Unit (ReLU) activation function in the analog domain for increased efficiency. The self-calibration is integrated into the data conversion process to minimize overheads and be fully online. The proposed activation neuron is designed and simulated using 22 nm FDSOI CMOS technology. The design demonstrates robustness across a wide temperature range (-40°C to 80°C) and under various process corners, with a maximum accuracy loss of 1 LSB for an 8-bit activation accuracy.

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Keywords

artificial neural networks, Edge AI, In-memory computing, on-chip PVT compensation, resistive cross-bars

DOI

10.1109/VLSI-SoC57769.2023.10321903

Citation

Numan, O, Andraud, M & Halonen, K 2023, A Self-Calibrated Activation Neuron Topology for Efficient Resistive-Based In-Memory Computing. in 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration, VLSI-SoC 2023. IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, IEEE, IEEE/IFIP International Conference on VLSI and System-on-Chip, Dubai, United Arab Emirates, 16/10/2023. https://doi.org/10.1109/VLSI-SoC57769.2023.10321903

Permanent link to this item

https://urn.fi/URN:NBN:fi:aalto-202401312271

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[article-cris] Sähkötekniikan korkeakoulu / ELEC

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A Self-Calibrated Activation Neuron Topology for Efficient Resistive-Based In-Memory Computing

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