Defect and yield analysis of semiconductor components and integrated circuits

Abstract

Semiconductors were studied from the point of material, component, electrical and functional properties. Several methods were used to accomplish this, e.g. X-ray topography, etch pit analysis, statistical methods, and neural nets.

The compound semiconductor components, i.e. GaAs varactor diodes, AlGaAs/InGaAs p-HEMTs, and LEDs (GaAs/AlGaAs and GaPN) were studied using the method of synchrotron X-ray topography.

First, the silicon wafers studied were selected from fully processed lots with varying, though, low yields. The electrical circuits were fabricated with a CMOS (Complementary Metal-Oxide Semiconductor) process, well suited for mixed-signal applications.

Then, synchrotron X-ray topographs and etch pit micrographs of the wafers were analyzed with an image processing software, written entirely for this study, to quantify the strain and defects present in the images. This information was then correlated with electrical parameters previously measured from the wafers, including the yield.

Several of the parameters quantified from the synchrotron X-ray images show a strong correlation with certain measured parameters, e.g. PMOS transistor threshold voltage, polysilicon sheet resistance, N- sheet contact chain resistance. Then, some parameters practically do not correlate, e.g. NMOS breakdown voltage. A strong correlation of device yield with near-surface strain measured by synchrotron X-ray topography is found.

Finally, the method of self-organizing map (SOM) neural net was applied to analyze a heartbeat rate monitor integrated circuit (IC) yield dependence on CMOS process control monitoring (PCM) data. The SOM efficiently reduces the PCM parameter space dimensions and helps in visualizing the different parameter relations. This makes it possible to identify the most probable PCM parameters affecting the yield. Those were found out to be NMOS transistor drain current and aluminum sheet resistance.