A 5.4-GHz 2/3/4-modulus fractional frequency divider circuit in 28-nm CMOS

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Conference article in proceedings
Date
2021
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Language
en
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2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings, IEEE International Symposium on Circuits and Systems proceedings
Abstract
This paper describes the design and post-layout simulations of a 2/3/4- modulus frequency divider circuit, accompanied with an accumulator that controls the division count. The circuit is capable of operating as an integer or as a fractional divider. Key topic of this paper is the merging of div-2/3 and div-3/4 circuits into a single compact circuit that solves an issue of a forbidden state in fractional-division operation. The circuit is designed with 28-nm CMOS technology and the post-layout simulations indicate an operating input frequency range of 0.3 - 5.4 GHz with 13-bit fractional frequency resolution between division ratios of 2-4. The divider occupies only 40 µm x 30 µm while consuming 2.0 mW at 5.4 GHz input frequency.
Description
Funding Information: This research has been financially supported by Academy of Finland (grant 2430226211). Publisher Copyright: © 2021 IEEE
Keywords
CMOS, Frequency division, Frequency synthesis, RFIC
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Citation
Cheung , T H , Ryynänen , J , Pärssinen , A & Stadius , K 2021 , A 5.4-GHz 2/3/4-modulus fractional frequency divider circuit in 28-nm CMOS . in 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings . , 9401405 , IEEE International Symposium on Circuits and Systems proceedings , IEEE , IEEE International Symposium on Circuits and Systems , Daegu , Korea, Republic of , 22/05/2021 . https://doi.org/10.1109/ISCAS51556.2021.9401405