Integrated Circuit Blocks for In-Memory Computing

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master_Numan_Omar_2020.pdf (20.96 MB)

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Sähkötekniikan korkeakoulu | Master's thesis
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Date

2020-10-19

Department

Major/Subject

Micro- and Nanoelectronic Circuit Design 2020-2022

Mcode

ELEC3036

Degree programme

Master’s Programme in Electronics and Nanotechnology (TS2013)

Language

en

Pages

11+84

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Abstract

There are several possible hardware implementations of neural networks based either on digital, analog, or analog-mixed-signal circuits. This thesis focuses on possible analog-mixed-signal integrated-circuit building blocks suitable for a $32\times 32$ analog vector-matrix multiplier that can execute the multiply-and-accumulate operations that happen within any neuromorphic computing engine in any artificial neural network. This process is known as analog in-memory computing, and it can solve many of the challenges associated with conventional digital computing neural network engines based on the von Neumann computer architecture. The building blocks that construct the core of the analog multiplier are designed and simulated in 65-nanometer CMOS technology to operate at a sampling frequency of 10 MHz with a 6-bit resolution. The thesis also discusses some characteristics of the presented circuit implementations and some trade-offs and issues identified in the reviewed integrated circuits. Moreover, this thesis discusses a brief review of some analog-only hardware implementations of neural networks. Furthermore, the thesis presents the peripheral circuits and data converters which support the in-memory computations—if not carefully designed; these circuits can significantly increase the energy, latency, and area consumption of the neural network. Finally, the thesis closes with some conclusions drawn from the analysis of the presented implementations.

Description

Supervisor

Halonen, Kari

Thesis advisor

Haapala, Tuomas

Keywords

neural networks, analog-mixed-signal integrated-circuit, vector-matrix multiplier, multiply-and-accumulate, in-memory computing, on Neumann architecture

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https://urn.fi/URN:NBN:fi:aalto-202010255990

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