Enhanced thermally aided memory performance using few-layer ReS 2 transistors

dc.contributorAalto-yliopistofi
dc.contributorAalto Universityen
dc.contributor.authorGoyal, Natashaen_US
dc.contributor.authorMacKenzie, David M.A.en_US
dc.contributor.authorPanchal, Vishalen_US
dc.contributor.authorJawa, Himanien_US
dc.contributor.authorKazakova, Olgaen_US
dc.contributor.authorPetersen, Dirch Hjorthen_US
dc.contributor.authorLodha, Saurabhen_US
dc.contributor.departmentIndian Institute of Technology Bombayen_US
dc.contributor.departmentDepartment of Electronics and Nanoengineeringen_US
dc.contributor.departmentNational Physical Laboratory (NPL)en_US
dc.contributor.departmentDanmarks Tekniske Universiteten_US
dc.date.accessioned2020-02-28T09:31:04Z
dc.date.available2020-02-28T09:31:04Z
dc.date.issued2020-02-03en_US
dc.description.abstractThermally varying hysteretic gate operation in few-layer ReS 2 and MoS 2 back gate field effect transistors (FETs) is studied and compared for memory applications. Clockwise hysteresis at room temperature and anti-clockwise hysteresis at higher temperature (373 K for ReS 2 and 400 K for MoS 2) are accompanied by step-like jumps in transfer curves for both forward and reverse voltage sweeps. Hence, a step-like conductance (STC) crossover hysteresis between the transfer curves for the two sweeps is observed at high temperature. Furthermore, memory parameters such as the RESET-to-WRITE window and READ window are defined and compared for clockwise hysteresis at low temperature and STC-type hysteresis at high temperature, showing better memory performance for ReS 2 FETs as compared to MoS 2 FETs. Smaller operating temperature and voltage along with larger READ and RESET-to-WRITE windows make ReS 2 FETs a better choice for thermally aided memory applications. Finally, temperature dependent Kelvin probe force microscopy measurements show decreasing (constant) surface potential with increasing temperature for ReS 2 (MoS 2). This indicates less effective intrinsic trapping at high temperature in ReS 2, leading to earlier occurrence of STC-type hysteresis in ReS 2 FETs as compared to MoS 2 FETs with increasing temperature.en
dc.description.versionPeer revieweden
dc.format.mimetypeapplication/pdfen_US
dc.identifier.citationGoyal , N , MacKenzie , D M A , Panchal , V , Jawa , H , Kazakova , O , Petersen , D H & Lodha , S 2020 , ' Enhanced thermally aided memory performance using few-layer ReS 2 transistors ' , Applied Physics Letters , vol. 116 , no. 5 , 052104 . https://doi.org/10.1063/1.5126809en
dc.identifier.doi10.1063/1.5126809en_US
dc.identifier.issn0003-6951
dc.identifier.issn1077-3118
dc.identifier.otherPURE UUID: f1e13911-929e-472a-9489-aeae54f391cben_US
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dc.identifier.otherPURE FILEURL: https://research.aalto.fi/files/41197036/ELEC_Goyal_Enhanced_thermally_APL.pdfen_US
dc.identifier.urihttps://aaltodoc.aalto.fi/handle/123456789/43270
dc.identifier.urnURN:NBN:fi:aalto-202002282319
dc.language.isoenen
dc.publisherAMER INST PHYSICS
dc.relation.ispartofseriesApplied Physics Lettersen
dc.relation.ispartofseriesVolume 116, issue 5en
dc.rightsopenAccessen
dc.titleEnhanced thermally aided memory performance using few-layer ReS 2 transistorsen
dc.typeA1 Alkuperäisartikkeli tieteellisessä aikakauslehdessäfi
dc.type.versionpublishedVersion
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