Enhanced thermally aided memory performance using few-layer ReS 2 transistors
Loading...
Access rights
openAccess
publishedVersion
URL
Journal Title
Journal ISSN
Volume Title
A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
This publication is imported from Aalto University research portal.
View publication in the Research portal (opens in new window)
View/Open full text file from the Research portal (opens in new window)
Other link related to publication (opens in new window)
View publication in the Research portal (opens in new window)
View/Open full text file from the Research portal (opens in new window)
Other link related to publication (opens in new window)
Date
2020-02-03
Major/Subject
Mcode
Degree programme
Language
en
Pages
5
Series
Applied Physics Letters, Volume 116, issue 5
Abstract
Thermally varying hysteretic gate operation in few-layer ReS 2 and MoS 2 back gate field effect transistors (FETs) is studied and compared for memory applications. Clockwise hysteresis at room temperature and anti-clockwise hysteresis at higher temperature (373 K for ReS 2 and 400 K for MoS 2) are accompanied by step-like jumps in transfer curves for both forward and reverse voltage sweeps. Hence, a step-like conductance (STC) crossover hysteresis between the transfer curves for the two sweeps is observed at high temperature. Furthermore, memory parameters such as the RESET-to-WRITE window and READ window are defined and compared for clockwise hysteresis at low temperature and STC-type hysteresis at high temperature, showing better memory performance for ReS 2 FETs as compared to MoS 2 FETs. Smaller operating temperature and voltage along with larger READ and RESET-to-WRITE windows make ReS 2 FETs a better choice for thermally aided memory applications. Finally, temperature dependent Kelvin probe force microscopy measurements show decreasing (constant) surface potential with increasing temperature for ReS 2 (MoS 2). This indicates less effective intrinsic trapping at high temperature in ReS 2, leading to earlier occurrence of STC-type hysteresis in ReS 2 FETs as compared to MoS 2 FETs with increasing temperature.Description
Keywords
Other note
Citation
Goyal, N, MacKenzie, D M A, Panchal, V, Jawa, H, Kazakova, O, Petersen, D H & Lodha, S 2020, ' Enhanced thermally aided memory performance using few-layer ReS 2 transistors ', Applied Physics Letters, vol. 116, no. 5, 052104 . https://doi.org/10.1063/1.5126809