Two-Dimensional Finite Impulse Response Filter Design Using Field Programmable Gate Arrays
dc.contributor | Aalto-yliopisto | fi |
dc.contributor | Aalto University | en |
dc.contributor.advisor | Alander, Jarmo | |
dc.contributor.author | Abdirahman, Hagi | |
dc.contributor.department | Automaatio- ja systeemitekniikan osasto | fi |
dc.contributor.school | Teknillinen korkeakoulu | fi |
dc.contributor.school | Helsinki University of Technology | en |
dc.contributor.supervisor | Hyötyniemi, Heikki | |
dc.date.accessioned | 2020-12-04T18:57:31Z | |
dc.date.available | 2020-12-04T18:57:31Z | |
dc.date.issued | 2004 | |
dc.format.extent | 49 s. + liitt. | |
dc.identifier.uri | https://aaltodoc.aalto.fi/handle/123456789/92133 | |
dc.identifier.urn | URN:NBN:fi:aalto-2020120450968 | |
dc.language.iso | en | en |
dc.programme.major | Systeemitekniikka | fi |
dc.programme.mcode | AS-74 | fi |
dc.rights.accesslevel | closedAccess | |
dc.subject.keyword | image processing | en |
dc.subject.keyword | image enhancement | en |
dc.subject.keyword | FIR | en |
dc.subject.keyword | FPGA | en |
dc.subject.keyword | ASIC | en |
dc.subject.keyword | DSP | en |
dc.subject.keyword | HDL | en |
dc.subject.keyword | block based design | en |
dc.subject.keyword | compute intensive | en |
dc.subject.keyword | parallel processing | en |
dc.subject.keyword | serial processing | en |
dc.title | Two-Dimensional Finite Impulse Response Filter Design Using Field Programmable Gate Arrays | en |
dc.type.okm | G2 Pro gradu, diplomityö | |
dc.type.ontasot | Master's thesis | en |
dc.type.ontasot | Pro gradu -tutkielma | fi |
dc.type.publication | masterThesis | |
local.aalto.digiauth | ask | |
local.aalto.digifolder | Aalto_90634 | |
local.aalto.idinssi | 26550 | |
local.aalto.openaccess | no |