All-parylene flexible wafer-scale graphene thin film transistor

dc.contributorAalto-yliopistofi
dc.contributorAalto Universityen
dc.contributor.authorKim, Mariaen_US
dc.contributor.authorMackenzie, David M.A.en_US
dc.contributor.authorKim, Wonjaeen_US
dc.contributor.authorIsakov, Kirillen_US
dc.contributor.authorLipsanen, Harrien_US
dc.contributor.departmentDepartment of Electronics and Nanoengineeringen
dc.contributor.groupauthorHarri Lipsanen Groupen
dc.date.accessioned2021-03-31T06:18:53Z
dc.date.available2021-03-31T06:18:53Z
dc.date.issued2021-06-15en_US
dc.description.abstractGraphene is an ideal candidate as a component of flexible/wearable electronics due to its two-dimensional nature and low gate bias requirements for high quality devices. However, the proven methods for fabrication of graphene thin film transistors (TFTs) on fixed substrates involve using a sacrificial polymer layer to transfer graphene to a desired surface have led to mixed results for flexible devices. Here, by using the same polymer layer (parylene C) for both graphene transfer and the flexible substrate itself, we produced graphene TFTs on the wafer-scale requiring less than |2 V| gate bias and with high mechanical resilience of 30,000 bending cycles.en
dc.description.versionPeer revieweden
dc.format.extent6
dc.format.mimetypeapplication/pdfen_US
dc.identifier.citationKim, M, Mackenzie, D M A, Kim, W, Isakov, K & Lipsanen, H 2021, 'All-parylene flexible wafer-scale graphene thin film transistor', Applied Surface Science, vol. 551, 149410. https://doi.org/10.1016/j.apsusc.2021.149410en
dc.identifier.doi10.1016/j.apsusc.2021.149410en_US
dc.identifier.issn0169-4332
dc.identifier.issn1873-5584
dc.identifier.otherPURE UUID: f687d287-8c3b-40f2-a9a1-7fb6eab86d43en_US
dc.identifier.otherPURE ITEMURL: https://research.aalto.fi/en/publications/f687d287-8c3b-40f2-a9a1-7fb6eab86d43en_US
dc.identifier.otherPURE FILEURL: https://research.aalto.fi/files/61199288/Kim_Allparylene_flexible_wafer_scale_graphene_thin_film_transistor.pdf
dc.identifier.urihttps://aaltodoc.aalto.fi/handle/123456789/103506
dc.identifier.urnURN:NBN:fi:aalto-202103312779
dc.language.isoenen
dc.publisherElsevier
dc.relation.fundinginfoThe research leading to these results received funding from the European Union Horizon 2020 Programme under grant agreement 696656 and 785219. We acknowledge also support from Academy of Finland under projects #1502002 and #13298297. Authors wishing to acknowledge assistance and encouragement colleagues Sanna Arpiainen and Miika Soikkeli from VTT Technical Research Center of Finland. This work was undertaken at the Micronova, Nanofabrication Center of Aalto University.
dc.relation.ispartofseriesApplied Surface Scienceen
dc.relation.ispartofseriesVolume 551en
dc.rightsopenAccessen
dc.subject.keywordFlexible electronicsen_US
dc.subject.keywordFlexible gate dielectricen_US
dc.subject.keywordGrapheneen_US
dc.subject.keywordParylene Cen_US
dc.subject.keywordTFTen_US
dc.subject.keywordThin film transistoren_US
dc.subject.keywordTwo-dimensional materialsen_US
dc.titleAll-parylene flexible wafer-scale graphene thin film transistoren
dc.typeA1 Alkuperäisartikkeli tieteellisessä aikakauslehdessäfi
dc.type.versionpublishedVersion

Files

Original bundle

Now showing 1 - 1 of 1
Loading...
Thumbnail Image
Name:
Kim_Allparylene_flexible_wafer_scale_graphene_thin_film_transistor.pdf
Size:
4.68 MB
Format:
Adobe Portable Document Format