A temperature and process compensation circuit for resistive-based in-memory computing arrays
Loading...
Access rights
openAccess
Journal Title
Journal ISSN
Volume Title
A4 Artikkeli konferenssijulkaisussa
This publication is imported from Aalto University research portal.
View publication in the Research portal
View/Open full text file from the Research portal
Other link related to publication
View publication in the Research portal
View/Open full text file from the Research portal
Other link related to publication
Date
2023
Major/Subject
Mcode
Degree programme
Language
en
Pages
Series
ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings, IEEE International Symposium on Circuits and Systems proceedings, Volume 2023-May
Abstract
In-Memory Computing (IMC) architectures promise increased energy-efficiency for embedded artificial intelligence. Many IMC circuits rely on analog computation, which is more sensitive to process and temperature variations than digital. Thus, maintaining a suitable computation accuracy may require process and temperature compensation. Focusing on resistive-based IMC architectures, we propose an ultra-low power circuit to compensate for the temperature and process-based non-linearities of resistive computing elements. The proposed circuit, implemented in 65 nm CMOS can provide a temperature coefficient between 10 and 1938 ppm/°C for a wide temperature range (-40°C to 80°C) and output current range (few pA up to 600 nA) at 1.2 V operating voltage. Used in a resistive IMC array, the variation of output currents from each multiply-accumulate (MAC) operation can be reduced by up to 84% to maintain computation accuracy across process and temperature variations.Description
Funding Information: ACKNOWLEDGMENTS This work is supported by Academy of Finland projects EHIR (grant 13334487) and WHISTLE (grant 332218) Publisher Copyright: © 2023 IEEE.
Keywords
In-memory computing, process compensation, Resistive random access memory, Thermal compensation, ultra-low power, variable temperature coefficient
Other note
Citation
Monga, D C, Numan, O, Andraud, M & Halonen, K 2023, A temperature and process compensation circuit for resistive-based in-memory computing arrays . in ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems, Proceedings . IEEE International Symposium on Circuits and Systems proceedings, vol. 2023-May, IEEE, IEEE International Symposium on Circuits and Systems, Monterey, California, United States, 21/05/2023 . https://doi.org/10.1109/ISCAS46773.2023.10181619
