L1 Cache and Memory Control for Multi-Core RISC-V Processors with MESI Protocol

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Sähkötekniikan korkeakoulu | Bachelor's thesis
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Date

2024-09-03

Department

Major/Subject

Digital Systems and Design

Mcode

ELEC3056

Degree programme

Aalto Bachelor's Programme in Science and Technology

Language

en

Pages

28

Series

Abstract

This thesis presents a comprehensive literature review on the design guidelines for cache coherence using the MESI protocol on multi-core systems, with extra emphasis on the design of the L1 cache and compatibility with the RISC-V ISA. Development of multi-core processors is the current direction of the industry and academia as the demand for computing power grows. High-performance multi-core systems require caches to facilitate fast access to large memory space. One of the main challenges in cache design on multi-core systems is cache coherence, which involves maintaining data consistency between local caches. The MESI protocol is a popular solution to this issue. However, the implementation of the MESI protocol involves various subtle details that designers should be mindful of. The thesis aims to support designers in managing these complexities. This work addresses the essence of cache design, cache coherence, and the MESI protocol. It also outlines recommendations for implementing cache and memory control for multi-core systems using the MESI protocol. The thesis can serve as a general guide for RISC-V system designers to approach cache design on multi-core systems.

Description

Supervisor

Ylirisku, Salu

Thesis advisor

Kosunen, Marko

Keywords

RISC-V, MESI protocol, multi-core, cache memory, L1 cache

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https://urn.fi/URN:NBN:fi:aalto-202411197168

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[kand] Sähkötekniikan korkeakoulu / ELEC