A 0.9-Nyquist-Band Digital Timing Mismatch Correction for Time-Interleaved ADCs Achieving Delay Tuning Range of 0.12-Sample-Period

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dc.contributorAalto-yliopistofi
dc.contributorAalto Universityen
dc.contributor.authorKempi, Iliaen_US
dc.contributor.authorJarvinen, Okkoen_US
dc.contributor.authorKosunen, Markoen_US
dc.contributor.authorUnnikrishnan, Vishnuen_US
dc.contributor.authorStadius, Karien_US
dc.contributor.authorRyynanen, Jussien_US
dc.contributor.departmentDepartment of Electronics and Nanoengineeringen
dc.contributor.groupauthorJussi Ryynänen Groupen
dc.date.accessioned2023-01-02T09:27:48Z
dc.date.available2023-01-02T09:27:48Z
dc.date.issued2022en_US
dc.descriptionPublisher Copyright: © 2022 IEEE.
dc.description.abstractTime-interleaved analog-to-digital converters (TIADC) require channel matching in terms of offset, gain, and sampling clock skew to achieve best data conversion performance. Conventionally, correction of skew mismatch is realized with analog delay lines, making it challenging for high-speed ADC designs to achieve fine delay resolution over wide tuning range while maintaining low clock jitter. Digital skew correction allows greater flexibility than analog solutions, but is hindered by a significant hardware footprint. This paper demonstrates digital filter-based timing skew correction approach suitable for on-chip implementation. In a 10-bit 8-channel TI-ADC the proposed structure corrects mismatch magnitudes up to 0.12 sample period across 0.9 Nyquist band while requiring only 65% hardware of similar architectures of equivalent performance. The presented digital circuit uses reduced combinational paths and operates at a clock rate of single ADC channel, making it applicable for digitally-assisted high-speed TI-ADCs.en
dc.description.versionPeer revieweden
dc.format.extent5
dc.format.extent929-933
dc.format.mimetypeapplication/pdfen_US
dc.identifier.citationKempi, I, Jarvinen, O, Kosunen, M, Unnikrishnan, V, Stadius, K & Ryynanen, J 2022, A 0.9-Nyquist-Band Digital Timing Mismatch Correction for Time-Interleaved ADCs Achieving Delay Tuning Range of 0.12-Sample-Period . in IEEE International Symposium on Circuits and Systems, ISCAS 2022 . IEEE International Symposium on Circuits and Systems proceedings, IEEE, pp. 929-933, IEEE International Symposium on Circuits and Systems, Austin, Texas, United States, 27/05/2022 . https://doi.org/10.1109/ISCAS48785.2022.9937669en
dc.identifier.doi10.1109/ISCAS48785.2022.9937669en_US
dc.identifier.isbn9781665484855
dc.identifier.issn0271-4302
dc.identifier.issn2158-1525
dc.identifier.otherPURE UUID: 448dfb4e-1af6-4f82-8a26-dfeb67528011en_US
dc.identifier.otherPURE ITEMURL: https://research.aalto.fi/en/publications/448dfb4e-1af6-4f82-8a26-dfeb67528011en_US
dc.identifier.otherPURE LINK: http://www.scopus.com/inward/record.url?scp=85142531933&partnerID=8YFLogxKen_US
dc.identifier.otherPURE FILEURL: https://research.aalto.fi/files/96138657/iscas22_paper1537_r2.pdfen_US
dc.identifier.urihttps://aaltodoc.aalto.fi/handle/123456789/118661
dc.identifier.urnURN:NBN:fi:aalto-202301021023
dc.language.isoenen
dc.relation.ispartofIEEE International Symposium on Circuits and Systemsen
dc.relation.ispartofseriesIEEE International Symposium on Circuits and Systems, ISCAS 2022en
dc.relation.ispartofseriesIEEE International Symposium on Circuits and Systems proceedingsen
dc.rightsopenAccessen
dc.titleA 0.9-Nyquist-Band Digital Timing Mismatch Correction for Time-Interleaved ADCs Achieving Delay Tuning Range of 0.12-Sample-Perioden
dc.typeA4 Artikkeli konferenssijulkaisussafi
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