A robust ultra-low voltage CPU utilizing timing-error prevention

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing.

Keywords

Clock stretching, Digital CMOS, Energy-efficiency, Near-threshold, Timing-error prevention (TEP), Ultra-low power (ULP), Variability

DOI

10.3390/jlpea5020057

Citation

Hiienkari, M, Teittinen, J, Koskinen, L, Turnquist, M, Mäkipää, J, Rantala, A, Sopanen, M & Kaltiokallio, M 2015, ' A robust ultra-low voltage CPU utilizing timing-error prevention ', Journal of Low Power Electronics and Applications, vol. 5, no. 2, pp. 57-68 . https://doi.org/10.3390/jlpea5020057

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https://urn.fi/URN:NBN:fi:aalto-201612216028

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[article-cris] Sähkötekniikan korkeakoulu / ELEC

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A robust ultra-low voltage CPU utilizing timing-error prevention

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