An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation
Loading...
Access rights
openAccess
URL
Journal Title
Journal ISSN
Volume Title
A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
This publication is imported from Aalto University research portal.
View publication in the Research portal (opens in new window)
View/Open full text file from the Research portal (opens in new window)
View publication in the Research portal (opens in new window)
View/Open full text file from the Research portal (opens in new window)
Date
2009
Department
Major/Subject
Mcode
Degree programme
Language
en
Pages
1-11
Series
EURASIP Journal on Advances in Signal Processing, Volume 2009
Abstract
A cellular analog processor array for use in variable block-size motion estimation with a new simple method for shifting reference image data is presented. The new shift method leads to a greatly reduced number of neighborhood connections for each cell of the array, and allows for all shifts within the [8,8] search area to be performed in a single step, with simple digital controls. The new shift circuitry, together with some other cell and system level optimizations, reduces silicon area and array layout complexity, enabling faster and more efficient parallel full search motion estimation hardware. A Open image in new window cell parallel analog test array for reference-shift with a maximum block-size of Open image in new window, as well as absolute value/quadratic processing for variable block-size analog motion estimation (AME) has been designed in a 0.13 Open image in new windowm CMOS technology.Description
Keywords
Other note
Citation
Poikonen , J , Laiho , M , Paasio , A , Koskinen , L & Halonen , K 2009 , ' An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation ' , Eurasip Journal on Advances in Signal Processing , vol. 2009 , 127630 , pp. 1-11 . https://doi.org/10.1155/2009/127630