Scheduling techniques in 5Gsystem on chip

Abstract

Currently, the 5G mobile network has received much attention due to the need for faster, more reliable, and more secure mobile communication. 5G uses cases have infiltrated every aspect of both daily and working life. Consequently, Multiple technologies, such as Network Function Virtualization (NFV) and Software Defined Networks (SDN) have been introduced to cope with the increasing user requirements.

Thanks to NFV and SDN, the networking elements moved from the traditional network elements, such as routers and switches; to virtualized network elements implemented on computing platforms, such as ARM or x86 CPUs. However, the rate of the network packet processing increase is much faster than the rate of performance increase in CPUs, especially with Moore's law reaching its end.

Hardware acceleration of network functions especially packet scheduling, has recently become the main solution for the gap between the CPU performance and the required processing speed for network packets. Additionally, software frameworks such as Open Data Plane (ODP) simplify the task of getting the network application running on these different platforms. As ODP offers a unified programming interface for high-performance data plane network applications.

This thesis aims to evaluate the feasibility of a packet scheduler as part of the future Nokia 5G chipset through ODP hardware accelerator prototype. This chipset aims to achieve high performance while maintaining a small size, low power, and low price. Then, this thesis compares various trade-offs, including the number of queues, priorities, scheduling algorithms, and memory type, either internal or external.