Design of 20-30 GHz CMOS Power Amplifier for Millimeter-wave Integrated Circuit

Thumbnail Image

URL

Journal Title

Journal ISSN

Volume Title

Sähkötekniikan korkeakoulu | Master's thesis

Authors

Date

2024-06-17

Department

Major/Subject

Micro- and Nanoelectronic Circuit Design

Mcode

ELEC3036

Degree programme

Master’s Programme in Electronics and Nanotechnology (TS2013)

Language

en

Pages

62

Series

Abstract

Recently, wireless communication systems have rapidly advanced towards millimeter-wave technology, aiming for higher integration, increased speed, and greater capacity. It has remained a formidable challenge to achieve a fully integrated single-chip radio system as many of the performance metrics and components influenced each other at very high frequencies. Our research group addresses these challenges by designing an integrated transceiver operating in the 20-30 GHz band in 28-nm CMOS technology. This transceiver includes a circulator, power amplifier, and low-noise amplifier sections implemented in both single-ended and differential structures with different antenna configurations and output impedances. This thesis focuses on designing the power amplifier, one of the most crucial building blocks in the RF transceivers. Successfully achieving output impedance matching, high linearity, high efficiency, and high output power requires careful and sophisticated design. In this study, a stacked amplifier structure is utilized as a power-combining technique to achieve high output power with low-voltage CMOS devices. A shunt-feedback drain-source capacitive node matching technique is employed to increase stacking efficiency by aligning the phase of impedances between stacked transistors. Additionally, a driver stage based on resistive feedback inverter structures is incorporated and designed. Post-layout simulations of the standalone PA revealed a peak gain of 26 dB at 25 GHz with a 3-dB bandwidth of 10 GHz. The PA achieved a saturated output power of 15.5 dBm and a maximum PAE of 17%. It maintained good performance across a wide frequency range, with an OP1dB of more than 12 dBm from 20 to 30 GHz. For the PA performance with circulator load, the single-ended 50 Ω and 18 Ω load designs achieved a peak gain of 22 dB at the center frequency and 3-dB bandwidth of 5.5 GHz. Lastly, the differential structure achieved a peak gain of 17.3 dB at 25 GHz and a 3-dB bandwidth of 7 GHz. While the gain is lower than single-ended designs, it offers a wider bandwidth. Compared to other state-of-the-art PAs, this design offers balanced performance with the most compact chip area of 0.0375 mm² and 0.0625 mm² for single-ended and differential design, respectively.

Description

Supervisor

Ryynänen, Jussi

Thesis advisor

Stadius, Kari

Keywords

power amplifier, CMOS, millimeter-wave nitegrated circuits, stacked power amplifier

Other note

Citation

Permanent link to this item

https://urn.fi/URN:NBN:fi:aalto-202406234890

Collections

[dipl] Sähkötekniikan korkeakoulu / ELEC