A Comprehensive Survey on Delaunay Triangulation : Applications, Algorithms, and Implementations Over CPUs, GPUs, and FPGAs
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A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
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Date
2024-01-26
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en
Pages
24
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IEEE Access, Volume 12, pp. 12562-12585
Abstract
Delaunay triangulation is an effective way to build a triangulation of a cloud of points, i.e., a partitioning of the points into simplices (triangles in 2D, tetrahedra in 3D, and so on), such that no two simplices overlap and every point in the set is a vertex of at least one simplex. Such a triangulation has been shown to have several interesting properties in terms of the structure of the simplices it constructs (e.g., maximising the minimum angle of the triangles in the bi-dimensional case) and has several critical applications in the contexts of computer graphics, computational geometry, mobile robotics or indoor localisation, to name a few application domains. This review paper revolves around three main pillars: (I) algorithms, (II) implementations over central processing units (CPUs), graphics processing units (GPUs), and field programmable gate arrays (FPGAs), and (III) applications. Specifically, the paper provides a comprehensive review of the main state-of-the-art algorithmic approaches to compute the Delaunay Triangulation. Subsequently, it delivers a critical review of implementations of Delaunay triangulation over CPUs, GPUs, and FPGAs. Finally, the paper covers a broad and multi-disciplinary range of possible applications of this technique.Description
Publisher Copyright: © 2013 IEEE.
Keywords
algorithmic approaches to Delaunay triangulation, applications of Delaunay triangulation, CPU, CPU implementation of Delaunay triangulation, Delaunay triangulation, FPGA, FPGA implementation of Delaunay triangulation, GPU, GPU implementation of Delaunay triangulation, Voronoi diagram
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Citation
Elshakhs, Y S, Deliparaschos, K M, Charalambous, T, Oliva, G & Zolotas, A 2024, ' A Comprehensive Survey on Delaunay Triangulation : Applications, Algorithms, and Implementations Over CPUs, GPUs, and FPGAs ', IEEE Access, vol. 12, pp. 12562-12585 . https://doi.org/10.1109/ACCESS.2024.3354709