Functional verification of frequency offset correction hardware accelerator IP used in beamforming multiplication module for 5G uplink SoC

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Journal Title

Journal ISSN

Volume Title

Sähkötekniikan korkeakoulu | Master's thesis

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Date

2024-05-20

Department

Major/Subject

Autonomous Systems

Mcode

ELEC3055

Degree programme

Master's Programme in ICT Innovation

Language

en

Pages

50

Series

Abstract

The increasing complexity of System-on-Chip (SoC) designs has significantly impacted both the time and financial resources for a dedicated verification process. Traditional verification methodologies and testbenches can not meet the demands of project development timeline. In this situation, verification engineers should adopt Universal Verification Methodology (UVM) to improve the efficiency of SoC design verification process cycle. SystemVerilog has become the primary language for SoC design verification due to its object-oriented programming characteristics and other advanced features. UVM based on SystemVerilog provides a set of standard libraries which can support constrained random testing, automatic comparison, and coverage-driven features. These advantages of UVM contribute to a more efficient verification environment. This thesis focuses on the verification of a frequency offset correction hardware accelerator Intellectual Property (IP) in Beamforming multiplication module used in a wireless communication baseband processor SoC. It begins with introduction of basic knowledge utilized in this thesis project and follows an in-depth analysis of current state of Soc design verification. Then it introduces functionalities and frame structure of the physical layer in 5th generation (5G) New Radio (NR) to elucidate the design specifications of the hardware accelerator IP. Based on the design specification, a verification plan and process are formulated. Utilizing UVM methodologies, the SoC verification platform is constructed. The study also incorporates coverage-driven methodologies combined with formal assertion-based verification techniques. The results with a code coverage of 45.14\% and a functional coverage of 41.78\% have met the established objectives for the first verification phase, thereby ensuring thoroughness and efficient progress in the verification process cycle. The analysis shows that the well-structured and efficient verification environment has improved debugging and efficiency. And the frequency offset correction hardware accelerator IP is verified in its first stage.

Description

Supervisor

Xiao, Yu

Thesis advisor

Vesalainen, Antti

Keywords

System-on-Chip (SoC, Universal Verification Methodology (UVM), hardware accelerator, testbench

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Citation

Permanent link to this item

https://urn.fi/URN:NBN:fi:aalto-202405263656

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[dipl] Sähkötekniikan korkeakoulu / ELEC