Design and implementation of high-speed multi-lane serial data receiver on Xilinx FPGA

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Sähkötekniikan korkeakoulu | Bachelor's thesis
Electronic archive copy is available locally at the Harald Herlin Learning Centre. The staff of Aalto University has access to the electronic bachelor's theses by logging into Aaltodoc with their personal Aalto user ID. Read more about the availability of the bachelor's theses.

Date

2018-01-03

Department

Major/Subject

Elektroniikka ja sähkötekniikka

Mcode

ELEC3013

Degree programme

Sähkötekniikan kandidaattiohjelma

Language

en

Pages

36

Series

Description

Supervisor

Turunen, Markus

Thesis advisor

Roverato, Enrico

Keywords

data transmission, serial, parallel, MGT, multi-gigabit transceiver, SerDes

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