Multithreading in Application Specific Instruction Set Processor

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Sähkötekniikan korkeakoulu | Master's thesis
Micro- and Nanoelectronic Circuit Design
Degree programme
Master’s Programme in Electronics and Nanotechnology (TS2013)
Application Specific Instruction Set Processor (ASIP) is an application domain-specific processor designed to obtain the maximum performance when executing a domain of particular applications. ASIPs have been increasingly studied and deployed into SoC chips needed for the fifth-generation (5G) wireless networks and even potential sixth-generation. That fact has led to a need for better performance, energy efficiency, and application flexibility. Furthermore, different architectures could be deployed on top of an ASIP to achieve a better performance ASIP. This work mentions three models: super pipelining, superscalar, and Very Long Instruction Word (VLIW). Each model is studied, resulting in advantages and disadvantages for each model in the ASIP deployment perspective. As a result, the author selects a VLIW model for the implementation. After that, the author performs a further performance study on the VLIW-based ASIP with multithreading. Multithreading is a traditional technique for tolerating latencies, improving functional unit utilization, and increasing instruction throughput. There are three models in multithreading: coarse-grained, simultaneous, and fine-grained. These models are studied, and a fine-grained multithreading model is chosen for the final implementation. In fine-grained multithreading, the processor switches to a new thread every cycle in a round-robin fashion. The implementation includes numerous changes to the existing register file, instructions, fetching, and controlling logic of the VLIW-based ASIP. In addition, the implementation introduces some new instructions and intrinsics to support writing programs for the multithreaded core. Benchmarking activity includes two tests for parsing ORAN messages. The results show that with multithreading when running these tests, there are significant speed-up in processing time (> 20% for the control plane and >10% for the user plane) in the case of a high number of sections per processed message. Regarding synthesis results, fine-grained multithreading implementation leads to an increase of 72% in the total processor area.
Ryynänen, Jussi
Thesis advisor
Kultala, Heikki
ASIP, SoC, VLIW, multihthreading, fine-grained multithreading