Dynamic element matching in digital-to-analog converters with non-linear output resistance
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Sähkötekniikan korkeakoulu |
Master's thesis
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Authors
Date
2017-01-23
Department
Major/Subject
Micro- and Nanoelectronic Circuit Design
Mcode
ELEC3036
Degree programme
NanoRad - Master’s Programme in Nano and Radio Sciences (TS2013)
Language
en
Pages
56+7
Series
Abstract
This thesis focuses on evaluating the performance of dynamic element matching in digital-to-analog converters, when the unit conversion cells of the converter have finite output resistance. The main goal of this thesis is to see the effect of the non-linearity introduced in the digital-to-analog converter's output, by the finite value of the output resistance and the mismatches in it and to realize if this non-linearity can be corrected by using the DEM encoder. This thesis considers the tree DEM encoder which is well known, in the literature, to be effective against amplitude and timing mismatches among different conversion cells. The available literature however doesn't consider the impact of finite output resistance. This thesis theorizes that since the DEM encoder scrambles the conversion cell order to correct the non-linearities, it will be ineffective against the output resistance as it is common to all the conversion cells. However, in the presence of output resistance mismatches, which exist between different conversion cells, DEM is again able to shape their non-linearity by scrambling. This thesis presents three conversion cell models with varying degrees of mismatches among the finite output resistances and derives the corresponding total output current expressions. In addition a MATLAB implementation of the most comprehensive model among the three derived models is also presented. The MATLAB simulation results show that the non-linearity caused by the output resistance, in the absence of any mismatches, is not shaped by the DEM encoder, however, in the presence of mismatches, the DEM encoder is able to shape the non-linearity. Also evident from the simulation results is that even very high order of mismatch in the output resistance doesn't significantly degrade the performance of the practical system we are using.Description
Supervisor
Ryynänen, JussiThesis advisor
Roverato, EnricoKeywords
CMOS, digital-to-analog converter (DAC), dynamic element matching (DEM), finite output resistance, mismatches