A wideband blocker-resilient direct delta sigma receiver with selective input-impedance matching

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Journal Title
Journal ISSN
Volume Title
A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
Date
2020-04-01
Major/Subject
Mcode
Degree programme
Language
en
Pages
13
195–207
Series
Analog Integrated Circuits and Signal Processing, Volume 103
Abstract
This paper presents a wideband blocker-tolerant direct DR receiver (DDSR). Blockers are attenuated through selective input impedance matching and reduced gain design. The selective input impedance profile provides a low impedance at blocker frequencies enabling blocker attenuation, while the in-band impedance is boosted to matched condition through an up-converted positive feedback from the DDSR output. In addition, with the help of reduced gain design, near band blocker gain is minimized, further improving the blocker resilience. The receiver is designed for configurable operation from 0.7-2.7 GHz and a baseband bandwidth of 10 MHz. Simulated in a 28 nm technology, the DDSR demonstrates a maximum noise figure of 6.2 dB, and achieves a peak SNDR of 53 dB with an out-of-band 1 dB input compression point of - 11 dBm at a 100 MHz offset.
Description
Keywords
Blocker tolerance, Selective impedance matching, Tunable bandpass filtering, Low noise amplifier, Direct delta sigma receiver, RF FRONT-END, ADC
Other note
Citation
Ul Haq , F , Englund , M , Östman , K B , Stadius , K , Kosunen , M , Koli , K & Ryynänen , J 2020 , ' A wideband blocker-resilient direct delta sigma receiver with selective input-impedance matching ' , Analog Integrated Circuits and Signal Processing , vol. 103 , no. 1 , pp. 195–207 . https://doi.org/10.1007/s10470-020-01611-2