A 2 GS/s 9-bit Time-Interleaved SAR ADC with Overlapping Conversion Steps

This paper presents a wideband 8-way time-interleaved (TI) 9-bit successive approximation register (SAR) analog-to-digital converter (ADC) with overlapping conversion steps that improve the speed of operation. The ADC generates its clocks using a synchronous counter based circuit which reduces the SAR delay. A common-mode reference based split capacitor array digital-to-analog converter (DAC) is implemented that achieves high speed and low power consumption. Simulation results are presented for the ADC designed in a 22 nm CMOS process. The TI ADC achieves at least 7.7 ENOB at 2 GS/s and consumes a total of 19.8 mW from 0.8 V supplies, resulting in 47.6 fF/conv-step. The single ADC achieves 8.34 ENOB at 250 MS/s, consuming 1.43 mW in total and 17.7 fF/conv-step.

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high-speed ADC, SAR ADC, time-interleaved ADC

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10.1109/NEWCAS52662.2022.9841992

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Tenhunen, M, Spoof, K, Unnikrishnan, V, Stadius, K, Kosunen, M & Ryynanen, J 2022, A 2 GS/s 9-bit Time-Interleaved SAR ADC with Overlapping Conversion Steps. in 20th IEEE International Interregional NEWCAS Conference, NEWCAS 2022 - Proceedings. IEEE, pp. 35-39, IEEE International New Circuits and Systems Conference, Quebec City, Canada, 19/06/2022. https://doi.org/10.1109/NEWCAS52662.2022.9841992

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https://urn.fi/URN:NBN:fi:aalto-202301181235

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[article-cris] Sähkötekniikan korkeakoulu / ELEC

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A 2 GS/s 9-bit Time-Interleaved SAR ADC with Overlapping Conversion Steps

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