A Blocker-Tolerant Two-Stage Harmonic-Rejection RF Front-End

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Date
2019
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Mcode
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Language
en
Pages
203-206
Series
IEEE Radio Frequency Integrated Circuits Symposium, IEEE Radio Frequency Integrated Circuits Symposium digest of papers
Abstract
SAW-less wideband receivers need to operate linearly in the presence of strong out-of-band blockers. In this paper, we introduce a blocker tolerant harmonic rejection RF front-end which is able to suppress blockers present at the local oscillator harmonics. The suppression is achieved by applying harmonic rejection in two stages, such that the first harmonic rejection already occurs at the output of LNA. The proposed front-end achieves this harmonic rejection with simpler 6-phase LO clocking and reduced number of base-band signal paths compared to 8-phase HR architectures. Further, the proposed design does not require any precise gain coefficients and implementing the harmonic rejection in two stages makes it more mismatch tolerant. In addition, near-band blocker linearity is improved by implementing a third order base-band feedback response which acts in conjunction with N-path filtering. Implemented in a 28nm FDSOI process, the front-end demonstrate 18-37dB harmonic rejection from the first stage and around46-53dB of harmonic rejection from the second stage with a state-of-the-art blocker compression point of 2.5dBm for a third harmonic blocker and a near-band blocker compression point of -6.5dBm.
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| openaire: EC/H2020/704947/EU//ADVANTAG5
Keywords
Harmonic rejection, blocker tolerance
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Citation
Ul Haq , F , Englund , M , Antonov , Y , Stadius , K , Kosunen , M , Östman , K , Koli , K & Ryynänen , J 2019 , A Blocker-Tolerant Two-Stage Harmonic-Rejection RF Front-End . in IEEE Radio Frequency Integrated Circuits Symposium . IEEE Radio Frequency Integrated Circuits Symposium digest of papers , IEEE , pp. 203-206 , IEEE Radio Frequency Integrated Circuits Symposium , Boston , Massachusetts , United States , 02/06/2019 . https://doi.org/10.1109/RFIC.2019.8701765