Applying residue number systems to hardware probability models

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master_Zhang_Peng_2024.pdf (1.63 MB)

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School of Electrical Engineering | Master's thesis
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Date

2024-11-19

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Major/Subject

Autonomous Systems

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Degree programme

Master's Programme in ICT Innovation

Language

en

Pages

64

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Abstract

The rapid advancement of machine learning, particularly in the realm of probabilistic models, faces challenges such as computational efficiency and accuracy. Deep neural networks (DNNs), while powerful and versatile, often lacks transparency and reasoning capabilities, making it less suitable for applications requiring clear decision-making processes. Probabilistic models, offering structured and interpretable systems for reasoning, present a promising alternative. However, accelerating these models remains a significant challenge due to their computational demands. This thesis investigates the application of Residue Number System (RNS) as an alternative to traditional fixed number systems for hardware-based probabilistic models. The research proposes an 8-moduli RNS-based approach to enhance parallel computation in Bayesian Networks (BNs). Through mathematical analysis and hardware implementation using Verilog and Vivado, the study demonstrates that RNS can significantly improve computational speed while maintaining acceptable accuracy. Error analysis and benchmarks reveal that RNS provides a competitive balance between performance and precision compared to 16-bit fixed-point and floating-point systems. The findings suggest that RNS is a viable and efficient alternative for applications requiring high-speed probabilistic inference, particularly in scenarios where numerical range and speed are critical.

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Supervisor

Zhou, Quan

Thesis advisor

Balaji Ravichandran, Naresh

Keywords

probabilistic models, Residue Number System (RNS), Bayesian Network (BN), hardware implementation, computational efficiency, FPGA

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https://urn.fi/URN:NBN:fi:aalto-202412167799

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