Bordered Block-Diagonal Preserved Model-Order Reduction for RLC Circuits

Thumbnail Image

Files

urn100463.pdf (745.45 KB)

URL

Journal Title

Journal ISSN

Volume Title

Master's thesis
Unless otherwise stated, all rights belong to the author. You may download, display and print this publication for Your own personal use. Commercial use is prohibited.

Authors

Date

2011

Department

Radiotieteen ja -tekniikan laitos

Major/Subject

Teoreettinen sähkötekniikka

Mcode

S-55

Degree programme

Language

en

Pages

[8] + 40

Series

Abstract

This thesis details the research of the bordered block-diagonal preserved model-order reduction (BVOR) method and implementation of the corresponding tool designed for facilitating the simulation of industrial, very large sized linear circuits or linear sub-circuits of a nonlinear circuit. The BVOR tool is able to extract the linear RLC parts of the circuit from any given typical SPICE netlist and perform reduction using an appropriate algorithm for optimum efficiency. The implemented algorithms in this tool are bordered block-diagonal matrix solver and bordered block-diagonal matrix based block Arnoldi method.

Description

Supervisor

Valtonen, Martti

Thesis advisor

Honkala, Mikko

Keywords

bordered block-diagonal preserved model-order reduction, RLC circuits, circuit simulation

Other note

Citation

Permanent link to this item

https://urn.fi/URN:NBN:fi:aalto-201207022689

Collections

[dipl] Sähkötekniikan korkeakoulu / ELEC