Bordered Block-Diagonal Preserved Model-Order Reduction for RLC Circuits

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Journal Title
Journal ISSN
Volume Title
Master's thesis
Author
Date
2011
Major/Subject
Teoreettinen sähkötekniikka
Mcode
S-55
Degree programme
Language
en
Pages
[8] + 40
Series
Abstract
This thesis details the research of the bordered block-diagonal preserved model-order reduction (BVOR) method and implementation of the corresponding tool designed for facilitating the simulation of industrial, very large sized linear circuits or linear sub-circuits of a nonlinear circuit. The BVOR tool is able to extract the linear RLC parts of the circuit from any given typical SPICE netlist and perform reduction using an appropriate algorithm for optimum efficiency. The implemented algorithms in this tool are bordered block-diagonal matrix solver and bordered block-diagonal matrix based block Arnoldi method.
Description
Supervisor
Valtonen, Martti
Thesis advisor
Honkala, Mikko
Keywords
bordered block-diagonal preserved model-order reduction, RLC circuits, circuit simulation
Other note
Citation