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An 8.62-μW 75-dB DRSoC Fully Integrated SoC for Spoken Language Understanding

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A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä

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en

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16

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IEEE Journal of Solid-State Circuits, Volume 60, issue 11, pp. 4002-4017

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We present a sub-10-µW fully integrated SoC for on-device spoken language understanding (SLU). Its analog feature extractor (FEx) applies global and per-channel automatic gain control (AGC) to extend the system’s dynamic range (DR)—a critical requirement for real-world scenarios, including far-field operations. The on-chip streaming-mode recurrent neural network (RNN) accelerator exploits temporal sparsity and pooling, reducing its power by 2.3x. By combining hardware-aware training with a behavioral model of the FEx that captures circuit nonidealities, the network is trained to maintain SLU accuracy despite chip-to-chip variation. Fabricated in a 65-nm CMOS process, the SoC occupies 2.23 mm 2 and consumes 8.62 µW for end-to-end SLU. The 16-channel FEx achieves 93-dB DR while dissipating 1.85 µW at 100-Hz feature frame rate. The SoC is evaluated on the 32-class Fluent Speech Commands dataset (FSCD), achieving 92.9% accuracy for 2.8-mV rms inputs while maintaining >85% accuracy over a 75-dB input range.

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Publisher Copyright: © 1966-2012 IEEE.

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Zhou, S, Li, Z, Cheng, L, Hadorn, J, Gao, C, Chen, Q, Delbruck, T, Kim, K & Liu, S C 2025, 'An 8.62-μW 75-dB DR SoC Fully Integrated SoC for Spoken Language Understanding', IEEE Journal of Solid-State Circuits, vol. 60, no. 11, pp. 4002-4017. https://doi.org/10.1109/JSSC.2025.3602936

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