The evolution of the Radio Access Network (RAN) has brought a massive architectural shift. The recent development of 5G seeks openness and a distributed nature, which disaggregates functions and components. 5G brings a new requirement that pushes the baseband computation towards the edge of commercial off-the-shelf (COTS) hardware with cloud-native deployment. To address the compute-intensive edge component, telcos are in front of utilising multiple hardware accelerators. Current computing architecture sees the memory of the accelerator in different address spaces. It brings challenges to efficient data communication between the host and the accelerator.
In this thesis, novel computing architecture, i.e. Memory-Driven Computing (MDC), is studied, analysed and discussed. This thesis implements the CXL, one of MDC’s industry-standard protocols. Compute Express Link (CXL) brings the host and accelerator memory into the load-store architecture, improving the communication between the host and the accelerator. The main idea of this implementation is to benchmark the CXL in comparison to regular memory and define the use case inRAN. In addition, this thesis implements the testbed with CXL type 2 memory and measures the throughput and latency. The results obtained from the measurement are promising in comparison to other remote memory access technology.
