A wideband blocker-resilient direct ΔΣ receiver with selective input-impedance matching

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Conference article in proceedings
Date
2017-09-25
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en
Pages
4
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IEEE International Symposium on Circuits and Systems, IEEE International Symposium on Circuits and Systems proceedings
Abstract
This paper presents a wideband blocker-tolerant Direct ΔΣ receiver (DDSR). Blockers are attenuated through selective input impedance matching and optimized gain design. The created impedance profile provides low receiver input impedance at blocker frequencies, while at desired frequencies, the impedance is boosted to matched condition through an up-converted positive feedback from the DDSR output. Receiver is evaluated in a 28nm fully-depleted silicon-on-insulator CMOS process with total power consumption of 25mW at 1V supply voltage. The receiver is designed for configurable operation from 0.7-2.7GHz, a baseband bandwidth of 10MHz, demonstrates a maximum noise figure of 6.2dB, and achieves a peak SNDR of 53dB with an out-of-band 1dB input compression point of -11.5dBm at 100MHz offset.
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Haq , F U , Englund , M , Stadius , K , Kosunen , M , Ryynanen , J , Koli , K & Ostman , K B 2017 , A wideband blocker-resilient direct ΔΣ receiver with selective input-impedance matching . in IEEE International Symposium on Circuits and Systems : From Dreams to Innovation, ISCAS 2017 - Conference Proceedings . , 8050249 , IEEE International Symposium on Circuits and Systems proceedings , IEEE , IEEE International Symposium on Circuits and Systems , Baltimore , Maryland , United States , 28/05/2017 . https://doi.org/10.1109/ISCAS.2017.8050249