Mixed-mode cellular array processor realization for analyzing brain electrical activity in epilepsy

dc.contributorAalto-yliopistofi
dc.contributorAalto Universityen
dc.contributor.authorLaiho, Mika
dc.contributor.departmentDepartment of Electrical and Communications Engineeringen
dc.contributor.departmentSähkö- ja tietoliikennetekniikan osastofi
dc.contributor.labElectronic Circuit Design Laboratoryen
dc.contributor.labPiiritekniikan laboratoriofi
dc.date.accessioned2012-02-10T08:52:38Z
dc.date.available2012-02-10T08:52:38Z
dc.date.issued2003-06-28
dc.description.abstractThis thesis deals with the realization of hardware that is capable of computing algorithms that can be described using the theory of polynomial cellular neural/nonlinear networks (CNNs). The goal is to meet the requirements of an algorithm for predicting the onset of an epileptic seizure. The analysis associated with this application requires extensive computation of data that consists of segments of brain electrical activity. Different types of computer architectures are overviewed. Since the algorithm requires operations in which data is manipulated locally, special emphasis is put on assessing different parallel architectures. An array computer is potentially able to perform local computational tasks effectively and rapidly. Based on the requirements of the algorithm, a mixed-mode CNN is proposed. A mixed-mode CNN combines analog and digital processing so that the couplings and the polynomial terms are implemented with analog blocks, whereas the integrator is digital. A/D and D/A converters are used to interface between the analog blocks and the integrator. Based on the mixed-mode CNN architecture a cellular array processor is realized. In the realized array processor the processing units are coupled with programmable polynomial (linear, quadratic and cubic) first neighborhood feedback terms. A 10 mm2, 1.027 million transistor cellular array processor, with 2×72 processing units and 36 layers of memory in each is manufactured using a 0.25 μm digital CMOS process. The array processor can perform gray-scale Heun's integration of spatial convolutions with linear, quadratic and cubic activation functions for 72×72 data while keeping all I/O operations during processing local. One complete Heun's iteration round takes 166.4 μs, while the power consumption during processing is 192 mW. Experimental results of statistical variations in the multipliers and polynomial circuits are shown. Descriptions regarding improvements in the design are also explained. The results of this thesis can be used to assess the suitability of the mixed-mode approach for implementing an implantable system for predicting epileptic seizures. The results can also be used to assess the suitability of the approach for implementing other applications.en
dc.description.versionrevieweden
dc.format.extent132
dc.format.mimetypeapplication/pdf
dc.identifier.isbn951-22-6598-2
dc.identifier.issn1455-8440
dc.identifier.urihttps://aaltodoc.aalto.fi/handle/123456789/2101
dc.identifier.urnurn:nbn:fi:tkk-000699
dc.language.isoenen
dc.publisherHelsinki University of Technologyen
dc.publisherTeknillinen korkeakoulufi
dc.relation.ispartofseriesReport / Helsinki University of Technology, Department of Electrical and Communications Engineering, Electronic Circuit Design Laboratoryen
dc.relation.ispartofseries38en
dc.subject.keywordmixed-mode integrated circuitsen
dc.subject.keywordanalog arithmetic circuitsen
dc.subject.keyword(polynomial) cellular neural/nonlinear networksen
dc.subject.keywordCMOSen
dc.subject.keyworddiscrete-time systemsen
dc.subject.keywordcellular array processorsen
dc.subject.otherMedical sciencesen
dc.subject.otherElectrical engineeringen
dc.titleMixed-mode cellular array processor realization for analyzing brain electrical activity in epilepsyen
dc.typeG4 Monografiaväitöskirjafi
dc.type.dcmitypetexten
dc.type.ontasotVäitöskirja (monografia)fi
dc.type.ontasotDoctoral dissertation (monograph)en
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