A 2.48 μ W 33.13 nV / √ Hz Instrumentation Amplifier for Bio-Impedance Sensors with Source Degenerated Current Mirror and DTMOS Transistor

Abstract

This paper introduces a low-power and low-noise instrumentation amplifier (IA) designed for bio-impedance sensing applications. Based on the noise analysis of a gain-boosted flipped voltage follower (FVF) transconductance (TC) stage, two noise reduction techniques are applied to the FVF circuit to optimize the input-referred noise contributions from the TC amplifier's input resistor (RIN ), input transistor (M1), and current source: (1) source degenerated current mirror (SDCM) and (2) dynamic threshold MOSFET (DTMOS). Additionally, a gain-boosted cascode structure is implemented in the feedback loop to enhance the loop gain. Simulated in the Cadence generic 45nm (gpdk045) CMOS process, the designed IA achieves a loop gain of 51.2 dB in the TC stage, an input-referred noise floor of 33.13 nV / √ Hz, and a bandwidth of 629 kHz, with a power consumption of 2.48 μ W under a 0.8 V supply. Compared to the baseline design, our low-noise approach achieves a 42.86% power saving. The design parameters of the IA are fully disclosed to facilitate replication and support further research.