Fully Digital On-Chip Wideband Background Calibration for Channel Mismatches in Time-Interleaved Time-Based ADCs

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Journal Title
Journal ISSN
Volume Title
A1 Alkuperäisartikkeli tieteellisessä aikakauslehdessä
Date
2022-01-24
Major/Subject
Mcode
Degree programme
Language
en
Pages
4
9-12
Series
IEEE Solid-State Circuits Letters, Volume 5
Abstract
This letter presents a fully integrated on-chip digital mismatch compensation system for time-based time-interleaved (TI) data converters. The proposed digital compensation features blind calibration of gain, offset, and timing mismatches. The implemented system uses time-based sampling clock mismatch detection, achieving convergence within 32K samples, which is on par with analog-assisted background methods. A specialized filter structure compensates for timing mismatches of magnitude up to 0.21 of the sampling period, nearly triple the range of other published digital compensation methods, and is effective for input signals up to 0.92 Nyquist bandwidth. The on-chip digital correction achieves suppression of all mismatch tones to levels below −60 dBc while running fully in the background. The operation is demonstrated with an 8× TI 2-GS/s analog-to-digital converter (ADC) prototype chip implemented in a 28-nm CMOS process.
Description
Keywords
time based, time interleaving, analog-to-digital converter (ADC), cyclic-coupled ring oscillator (CCRO), digital calibration, finite-impulse response (FIR), least mean-square (LMS), mismatch, timing skew
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Citation
Jarvinen , O , Kempi , I , Unnikrishnan , V , Stadius , K , Kosunen , M & Ryynänen , J 2022 , ' Fully Digital On-Chip Wideband Background Calibration for Channel Mismatches in Time-Interleaved Time-Based ADCs ' , IEEE Solid-State Circuits Letters , vol. 5 , pp. 9-12 . https://doi.org/10.1109/LSSC.2022.3145918