Integrated Circuit design of Semi-Passive Near Field Communication
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Journal Title
Journal ISSN
Volume Title
Sähkötekniikan korkeakoulu |
Master's thesis
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Author
Date
2024-05-20
Department
Major/Subject
Micro- and Nanoelectronic Circuit Design
Mcode
ELEC3036
Degree programme
Master’s Programme in Electronics and Nanotechnology (TS2013)
Language
en
Pages
65
Series
Abstract
This thesis emphasizes the design of analog front-end and digital circuits for the on-chip implementation of Near Field Communication (NFC) chip based on the ISO/IEC 15693 protocol. The circuit is designed in 65 nm bulk Complementary metal-oxide-semiconductor (CMOS) technology using Cadence Virtuoso environment for circuit design and the Spectre simulator for emulation. Simulations are performed for equivalent antennas, voltage limiter circuits, low modulation index (MI) Amplitude Shift Keying (ASK) demodulators, level shifting circuits using Radio-frequency (RF) inputs, and equivalent antennas under various process corners and temperatures to analyze the behavior. A low-power ASK demodulator is designed with a low modulation index of 1.12\%. The discourse on load modulation considers both resistive and capacitive modulators, culminating in a spectral analysis at low coupling coefficients $k$, to verify the functionality of backscatter communication. Voltage limiters effectively constraint tens of resonant volts to a maximum of 2.5 V, ensuring the operational efficiency of the system at a temperature range of 0--50 degrees. The digital module design is validated on both application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) platforms. The 1 out of 4 pulse-position modulation is used to design decoder and the parallel-working Cyclic Redundancy Check (CRC-16) by incorporating error detection mechanisms through a Linear Feedback Shift Register (LFSR) for parity checks and cyclic redundancy checks. The encoder utilizes the Manchester coding to encode the output of the multipurpose processor. The details of design area and the post-layout simulation results of power consumption and timing are presented and discussed for both ASIC and FPGA implementations. A low power consumption of 0.1618 mW and an efficient area of 165 um x 165 um is achieved for the ASIC implementation of the proposed design. Whereas the effective design implementation on the Virtex-7 VC707 Evaluation Platform consumes power of 2.57 mW.Description
Supervisor
Halonen, KariThesis advisor
Muhammad, TanweerKeywords
HF RFID tag, analog front-end, ASK demodulator, load modulator
