Open-loop all-digital delay line with on-chip calibration via self-equalizing delays

A novel calibration technique and its all-digital implementation for the open-loop delay line is presented. Fully autonomous approach iteratively compares each digitally-controlled delay stage of the line with an on-chip reference delay, correspondingly tuning selected stage and memorizing associated settings. After correcting all individual stages, the total delay of the line is compared with the external period and reference delay is then readjusted. When on-board settling monitor observes repetition of reference delay settings, it locks delay line by applying previously collected settings. The delay line is shown to lock in presence of 30% static offset of delays from their designed values. Furthermore, random spread of delays worsened by 3 times (5% PP to 15% PP ) results in only 2% decline (3% PP to 5% PP ) after applying the proposed calibration to 16-delays line.

DOI

10.1109/ECCTD.2017.8093344

Citation

Antonov, Y, Stadius, K, Kosunen, M & Ryynänen, J 2017, Open-loop all-digital delay line with on-chip calibration via self-equalizing delays. in 23rd European Conference on Circuit Theory and Design (ECCTD 2017). European Conference on Circuit Theory and Design, IEEE, pp. 1-4, European Conference on Circuit Theory and Design, Catania, Italy, 04/09/2017. https://doi.org/10.1109/ECCTD.2017.8093344

Permanent link to this item

https://urn.fi/URN:NBN:fi:aalto-202203162257

Collections

[article-cris] Sähkötekniikan korkeakoulu / ELEC

Show all metadata

Open-loop all-digital delay line with on-chip calibration via self-equalizing delays

Access rights

URL

Journal Title

Journal ISSN

Volume Title

Authors

Date

Department

Major/Subject

Mcode

Degree programme

Language

Pages

Series

Abstract

Description

Keywords

Other note

DOI

Citation

Permanent link to this item

Collections