Simulation of the digital phase locked loop in the time domain
dc.contributor | Aalto-yliopisto | fi |
dc.contributor | Aalto University | en |
dc.contributor.author | Rinne, Mikko | |
dc.contributor.department | Sähkötekniikan osasto | fi |
dc.contributor.school | Teknillinen korkeakoulu | fi |
dc.contributor.school | Helsinki University of Technology | en |
dc.contributor.supervisor | Porra, Veikko | |
dc.date.accessioned | 2020-12-03T18:23:43Z | |
dc.date.available | 2020-12-03T18:23:43Z | |
dc.date.issued | 1994 | |
dc.format.extent | 48 | |
dc.identifier.uri | https://aaltodoc.aalto.fi/handle/123456789/82573 | |
dc.identifier.urn | URN:NBN:fi:aalto-2020120341411 | |
dc.language.iso | fi | en |
dc.programme.major | Piiritekniikka | fi |
dc.programme.mcode | S-87 | fi |
dc.rights.accesslevel | closedAccess | |
dc.subject.keyword | phase locked loop | en |
dc.subject.keyword | vaihelukittu silmukka | fi |
dc.subject.keyword | digital phase lock | en |
dc.subject.keyword | digitaalinen vaihelukko | fi |
dc.subject.keyword | frequency synthesis | en |
dc.subject.keyword | taajuussynteesi | fi |
dc.subject.keyword | simulation | en |
dc.subject.keyword | simulointi | fi |
dc.subject.keyword | CAE | en |
dc.subject.keyword | CAE | fi |
dc.title | Simulation of the digital phase locked loop in the time domain | en |
dc.title | Digitaalisen vaihelukon simulointi aika-alueessa | fi |
dc.type.okm | G2 Pro gradu, diplomityö | |
dc.type.ontasot | Master's thesis | en |
dc.type.ontasot | Pro gradu -tutkielma | fi |
dc.type.publication | masterThesis | |
local.aalto.digiauth | ask | |
local.aalto.digifolder | Aalto_39295 | |
local.aalto.idinssi | 9447 | |
local.aalto.openaccess | no |