Integrated clock gating analysis and optimization to improve the properties of clock tree structure in integrated circuit

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master_Vo_Tai_2024.pdf (25.47 MB)

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School of Electrical Engineering | Master's thesis
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Date

2024-11-18

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Major/Subject

Microelectronic Circuit Design

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Degree programme

Master's Programme in Electronics and Nanotechnology

Language

en

Pages

72

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Abstract

The growing demand for low-power integrated circuits has made power reduction techniques. Among these techniques, clock gating is an essential method to use in modern electronic devices to reduce dynamic power consumption. Integrated clock gating offers a more efficient way to control power by embedding clock control logic directly into the circuit, reducing unnecessary clock activity. However, implementing integrated clock gating presents challenges, particularly in critical timing control to meet enable logic setup requirements. This thesis investigates the impact of integrated clock gating on the clock tree structure, focusing on timing, power, area, and latency. It aims to develop optimization methods that enhance critical enable setup timing while balancing trade-offs in power and area. The research examines optimization techniques applied at both the logic synthesis and layout level implementation to improve the efficiency of clock gating systems. The findings of this thesis demonstrate that by applying targeted optimizations, significant improvements in timing control to clock gating setup can be achieved without much negative impact to power savings and efficient area utilization. In addition, advanced techniques, such as equivalence checking and useful skew adjustments, are to ensure reliability and provide sign-off timing solutions in low-power designs with clock gating.

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Supervisor

Ryynänen, Jussi

Thesis advisor

Punkka, Konsta

Keywords

clock tree synthesis, equivalence checking, integrated clock gating, logic synthesis, power reduction, static timing analysis

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https://urn.fi/URN:NBN:fi:aalto-202412167795

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[dipl] Sähkötekniikan korkeakoulu / ELEC