An integrated low voltage 150Mbit/s cable communication circuit and a CMOS clock recovery phase and frequency locked loop
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Helsinki University of Technology |
Licentiate thesis
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Instructions for the author
Authors
Date
1998
Department
Major/Subject
Piiritekniikka
Mcode
S-87
Degree programme
Language
en
Pages
58
Series
Description
Supervisor
Halonen, KariThesis advisor
Koli, KimmoKeywords
Jitter, Jitteri, PLL, kuollut alue, dead zone, korjain, equalizer, prosessi ja lämpötila hajonnat, process and temperature variations, matala käyttöjännite, low voltage