Digital Phase Locked Loop Circuits Used for 2 Mbit/s Synchronization Ports in an SDH Access Node

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Volume Title

Helsinki University of Technology | Master's thesis
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P1 Ark TKK

Authors

Date

2000

Department

Sähkö- ja tietoliikennetekniikan osasto

Major/Subject

Tietoliikennetekniikka

Mcode

S-72

Degree programme

Language

en

Pages

xi + 92

Series

Description

Supervisor

Halme, Seppo J.

Thesis advisor

Schrod, Rolf

Keywords

digital phase-locked loop, digitaalinen vaihelukko, PLL, synkronointi, synchronization, värinä, jitter, näytteenotto, sampling, synkroninen digitaalinen hierarkia, synchronous digital hierarchy, SDH

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Citation

Permanent link to this item

https://urn.fi/URN:NBN:fi:aalto-2020120446797

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[dipl] Teknillinen korkeakoulu / TKK