Digital Phase Locked Loop Circuits Used for 2 Mbit/s Synchronization Ports in an SDH Access Node
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Helsinki University of Technology |
Diplomityö
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Instructions for the author
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Date
2000
Department
Major/Subject
Tietoliikennetekniikka
Mcode
S-72
Degree programme
Language
en
Pages
xi + 92
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Description
Supervisor
Halme, Seppo J.Thesis advisor
Schrod, RolfKeywords
digital phase-locked loop, digitaalinen vaihelukko, PLL, synkronointi, synchronization, värinä, jitter, näytteenotto, sampling, synkroninen digitaalinen hierarkia, synchronous digital hierarchy, SDH