Automatic Hardware-aware Optimization of Fault-tolerant Quantum Circuits

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Perustieteiden korkeakoulu | Bachelor's thesis
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Date

2024-04-26

Department

Major/Subject

Quantum Technology

Mcode

SCI3103

Degree programme

Aalto Bachelor’s Programme in Science and Technology

Language

en

Pages

27+6

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Abstract

This thesis explores the calibration of quantum error correction codes (QECC) by focusing on optimizing plaquette circuits at the native gate level and assessing their error rates on real quantum hardware. The research underscores the importance of native gate optimization to boost the performance and reliability of quantum computations. A crucial part of the study involves experiments on the repetition of plaquette circuits using two ancilla qubit configurations: Type A, involving fresh ancilla qubits for each repetition, and Type B, reusing ancilla qubits. Based on the data collected, an error model was formulated. A significant result is that the error rate for a single plaquette operation using IonQ’s Aria1 Quantum Processing Unit (QPU) was 1.5%, surpassing the essential 1% threshold for effective quantum error correction, thus indicating a need for further improvements. The thesis also demonstrates the variability in QECC implementation across different quantum architectures, emphasizing the challenges in establishing universally applicable error rates. The study proposes to extend this research to evaluate the error rates of plaquette circuits on other types of quantum hardware, such as superconducting quantum computers. Future work will develop a broader understanding of QECC’s effective implementation across various quantum computing platforms, enhancing the robustness and scalability of quantum error correction methods.

Description

Supervisor

Raasakka, Matti

Thesis advisor

Paler, Alexandru

Keywords

quantum circuits, quantum error correction, optimization, physical gates, error rate, surface code

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https://urn.fi/URN:NBN:fi:aalto-202406184543

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[kand] Perustieteiden korkeakoulu / SCI