Fractional-N open-loop digital frequency synthesizer with a post-modulator for jitter reduction
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A4 Artikkeli konferenssijulkaisussa
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Date
2016-07-08
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Language
en
Pages
4
130-133
130-133
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RFIC 2016 - 2016 IEEE Radio Frequency Integrated Circuits Symposium, IEEE Radio Frequency Integrated Circuits Symposium
Abstract
This paper presents a 0.4 to 2.1 GHz open-loop fractional-N multiplying delay-locked loop based frequency synthesizer in 65 nm CMOS. The proposed frequency synthesizer architecture is based on Digital Period Synthesis that features wide frequency range, fine frequency resolution, instantaneous frequency switching and is capable to provide several independent outputs. An inherent challenge of fractional-N synthesis is a notable deterministic jitter. In this paper we present a high-speed direct delay modulation circuit (DDM) that provides over ten-fold reduction in deterministic jitter over the entire frequency range. The measured deterministic period jitter, related to the fractional mode operation, is reduced from 51 ps to 4 ps by using the DDM. Furthermore, in this paper we demonstrate, for the first time, how the implemented synthesizer can produce two totally independent outputs at different frequencies.Description
Keywords
delay modulator, fractional-N frequency synthesizer, multiplying delay-locked loop (MDLL)
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Citation
Rapinoja, T, Antonov, Y, Stadius, K & Ryynänen, J 2016, Fractional-N open-loop digital frequency synthesizer with a post-modulator for jitter reduction . in RFIC 2016 - 2016 IEEE Radio Frequency Integrated Circuits Symposium ., 7508268, IEEE Radio Frequency Integrated Circuits Symposium, IEEE, pp. 130-133, IEEE Radio Frequency Integrated Circuits Symposium, San Francisco, United States, 22/05/2016 . https://doi.org/10.1109/RFIC.2016.7508268