Power Profiling Model for RISC-V Core
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Sähkötekniikan korkeakoulu |
Master's thesis
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Authors
Date
2023-06-12
Department
Major/Subject
Micro- and Nanoelectronic Circuit Design
Mcode
ELEC3036
Degree programme
Master’s Programme in Electronics and Nanotechnology (TS2013)
Language
en
Pages
58+4
Series
Abstract
The reduction of power consumption is considered to be a critical factor for efficient computation of microprocessors. Therefore, it is necessary to implement a power management system that is aware of the computational load of the CPU cores. To enable such power management, this project aims to develop a power profiling model for the RISC-V core. TheSyDeKick verification environment was used to develop the power profiling models. Additionally, Python-controlled mixed mode simulations of C-programs compiled for A-Core were conducted to obtain needed data for the power profiling of the digital circuitry. The proposed methodology could employ a time-varying power consumption profiling for the A-Core RISC-V microprocessor core which depends on software, voltage, and clock frequency. The results of this project allow for the creation of parameterized power profiles for the A-Core, which can contribute to more efficient and sustainable computing.Description
Supervisor
Ryynänen, JussiThesis advisor
Kosunen, MarkoKeywords
RISC-V, power profiling, power management, TheSyDeKick