Power profiling model for RISC-V core

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master_Zhang_Lin_2023.pdf (6.89 MB)

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Sähkötekniikan korkeakoulu | Master's thesis
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Date

2023-06-12

Department

Major/Subject

Micro- and Nanoelectronic Circuit Design

Mcode

ELEC3036

Degree programme

Master’s Programme in Electronics and Nanotechnology (TS2013)

Language

en

Pages

58+4

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Abstract

The reduction of power consumption is considered to be a critical factor for efficient computation of microprocessors. Therefore, it is necessary to implement a power management system that is aware of the computational load of the CPU cores. To enable such power management, this project aims to develop a power profiling model for the RISC-V core. TheSyDeKick verification environment was used to develop the power profiling models. Additionally, Python-controlled mixed mode simulations of C-programs compiled for A-Core were conducted to obtain needed data for the power profiling of the digital circuitry. The proposed methodology could employ a time-varying power consumption profiling for the A-Core RISC-V microprocessor core which depends on software, voltage, and clock frequency. The results of this project allow for the creation of parameterized power profiles for the A-Core, which can contribute to more efficient and sustainable computing.

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Supervisor

Ryynänen, Jussi

Thesis advisor

Kosunen, Marko

Keywords

RISC-V, power profiling, power management, TheSyDeKick

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https://urn.fi/URN:NBN:fi:aalto-202306183988

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[dipl] Sähkötekniikan korkeakoulu / ELEC