A Clock-Tunable Dynamic Current Reference with a Built-In 2nd-Order Current-Mode Low-Pass Filter and Coarse-Fine Regulation

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School of Electrical Engineering | Master's thesis

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Mcode

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en

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62

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This thesis presents the design and implementation of a frequency-controlled nano-ampere current reference (IREF) circuit capable of generating reconfigurable output currents. Based on the proposed topology, two approaches distinguished by the MOSFET threshold voltage (Vth) are explored: RVT (regular Vth) and LVT (low Vth). Both implementations were designed and simulated using the Cadence generic 45 nm (gpdk045) CMOS process technology. The RVT-based approach offers a low supply voltage (VDD) range (0.9 V to 1.6 V) with line sensitivity (LS ) to be 4.14 %/V. It operates with a current range from 1.6 nA to 72 nA, with a temperature coefficient (TC ) of 220.6 ppm/°C over the temperature range of -40 °C to 125 °C. In contrast, the LVT-based approach produces an IREF from 2.3 nA to 205 nA but demonstrates a much better TC of 47.2 ppm/°C within -40 °C to 125 °C. It requires a higher VDD from 1.1 V to 2 V but the LS is reduced to 1.23 %/V by increasing channel length. Both approaches do not require any trimming or calibration. To ensure stable current generation, the design incorporates a 2nd-order current-mode low pass filter (LPF ) that effectively suppresses current ripples to below 0.2 % peak-to-peak within the whole frequency range for both approaches. The thesis provides comprehensive analysis of the circuit design methodology, detailed simulation results, and complete design parameter specifications to enable reproducibility and support future research in the field of low-power current reference circuits. The wide current range combined with low ripple performance makes the design particularly suitable for low-power applications and contributes to the advancement of dynamic and scalable analog circuits for emerging low-power electronic systems.

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Kim, Kwantae

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