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Efficient Time-Domain Simulation of Interconnects Characterized by Large RLC Circuits or Tabulated S Parameters

Helsinki University of Technology | Licentiate thesis

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Authors

Date

Department

Sähkö- ja tietoliikennetekniikan osasto

Major/Subject

Teoreettinen sähkötekniikka

Mcode

S-55

Language

en

Pages

92

Supervisor

Valtonen, Martti

Thesis advisor

Roos, Janne

Keywords

circuit simulation, piirisimulointi, interconnect simulation, interconnect-simulointi, model-order reduction, malliredusointi, frequency-domain model, taajuusalueen malli, transient analysis, transienttianalyysi, APLAC, APLAC

Permanent link to this item

https://urn.fi/URN:NBN:fi:aalto-202104155688

Collections

[lic] Teknillinen korkeakoulu / TKK

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