Efficient Time-Domain Simulation of Interconnects Characterized by Large RLC Circuits or Tabulated S Parameters

No Thumbnail Available
Journal Title
Journal ISSN
Volume Title
Helsinki University of Technology | Licentiate thesis
Checking the digitized thesis and permission for publishing
Instructions for the author
Date
2004
Major/Subject
Teoreettinen sähkötekniikka
Mcode
S-55
Degree programme
Language
en
Pages
92
Series
Description
Supervisor
Valtonen, Martti
Thesis advisor
Roos, Janne
Keywords
circuit simulation, piirisimulointi, interconnect simulation, interconnect-simulointi, model-order reduction, malliredusointi, frequency-domain model, taajuusalueen malli, transient analysis, transienttianalyysi, APLAC, APLAC
Other note
Citation