Integrated Radio-Frequency Receivers for RF-to-Digital Converters

Abstract

The widespread usage of mobile communication in recent decades has crowded the frequency spectrum with multiple bands and communication standards. An ideal wireless receiver for such a scenario will need to cover all frequency bands/standards with the possibility of instant reconfigurability through software control. The receiver should also be entirely integrated to gain the advantages of mobility and cheaper production costs. The ultimate goal of an ideal receiver is encapsulated in the concept of software-defined radio (SDR). An attractive approach to realize an SDR is an RF-to-digital converter. In best case, an RF-to-digital converter consists of an analog-to-digital converter (ADC) which is directly connected to a wideband antenna. This means that the received signal on the antenna is immediately converted in the digital domain where reconfigurability is easy to achieve. However, such a complete RF-to-digital converter has so far proved to be an elusive goal due to impractically high power consumption requirements of ADC in the GHz range. Therefore, a practical RF-to-digital converter is followed by an RF front-end which reduces the power consumption requirements of an ADC by signal amplification, filtering, and frequency down-conversion. SDR research for such a practical case is focused towards reconfigurable, wideband and digital intensive RF front-ends. It is also targetted at reducing the number of parallel receiver front-ends by implementing a single wideband and fully integrated front-end capable of receiving all frequency bands/standards. To design receiver solutions for such a practical RF-to-digital converter, new techniques are needed to overcome the design challenges. This thesis focuses on finding new solutions to four of these design challenges related to the goal of RF-to-digital converters: 1) Blocker tolerance in wideband RF front-ends; 2) harmonic rejection RF-front ends with on-chip N-path filtering; 3) transmitter self leakage cancellation, and; 4) blocker rejection and sensitivity issues in direct delta sigma receivers. Starting from the detailed description of these challenges, research outcomes on both theoretical and experimental fronts are presented. In particular, a harmonic-rejection receiver was fabricated in 28nm fully-depleted silicon-on-insulator (FDSOI) technology. The receiver attempts to resolve many of the above-mentioned challenges through higher-order on-chip filtering, simple local-oscillator clocking, and a two-stage harmonic-rejection implementation. The receiver front-end also includes a novel transmitter signal-leakage cancellation technique through buried-gate signaling in an FDSOI process. In addition to the fabricated receiver, the thesis incorporates two new blocker attenuation techniques at the input of the low-noise amplifier in the receiver chain. On the theoretical front, sensitivity issues in direct delta sigma receivers are analyzed with detailed theoretical modeling leading to simple design guidelines. Details of all these contributions can be found in the author's publications I-IX.