Low-power and high-fanout bus design techniques
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Journal Title
Journal ISSN
Volume Title
Sähkötekniikan korkeakoulu |
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Authors
Date
2014-06-16
Department
Major/Subject
Micro and Nanotechnology
Mcode
S3010
Degree programme
EST - Master’s Programme in Micro and Nanotechnology
Language
en
Pages
66+7
Series
Abstract
Low-power techniques pose an important concern, when designing autonomous electronic devices. Most of the upcoming applications increasingly demand high performance and low-power consumption. In this thesis work, two low-power and high-fanout bus design techniques are reviewed. Pulse Width Modulation (PWM) and Time-Domain Conversion (TDC) approaches are elucidated. Schematic simulations (Cadence), quantitative and comparative results of both approaches are included. Additionally, on-chip wire theory is shown as well as some optimized bus simulation models (MATLAB), concluding with a summary of the main application areas for this techniques. Finally , two ready-to-use library cells are generated, as well as Verilog code for the TDC system.Description
Supervisor
Ryynänen, JussiThesis advisor
Koskinen, LauriKeywords
low-power, high-fanout, bus, hardware neural networks, network-on-chip, pulse width modulation, time-domain, pulse, width modulation, wire model, repeater