Implementation of a measurement system for gate oxide integrity characterization
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Journal Title
Journal ISSN
Volume Title
Sähkötekniikan korkeakoulu |
Master's thesis
Authors
Date
2024-08-19
Department
Major/Subject
Smart Systems Integrated Solutions
Mcode
ELEC3064
Degree programme
Master’s Programme in Smart Systems Integrated Solutions (Erasmus Mundus)
Language
en
Pages
37+7
Series
Abstract
Gate oxide is an important thin-film layer in modern transistor architecture because of its excellent insulating property. However, defects that originate from various manufacturing processes can negatively impact the gate oxide and its integrity with other materials. These defects reduce the dielectric strength of the gate oxide and are responsible for it becoming conductive. Therefore, it is crucial to measure and identify these defects properly for the quality improvement of the semiconductor devices. This thesis presents the design and implement of a gate oxide integrity (GOI) measurement system that can accurately detect defects and determine the defect density of gate oxide on the silicon wafer. Primarily, in the literature review, we identify that the voltage ramp stress test is the optimal method to accomplish our aims, as it can be used to detect the defects within the oxide film and its interfaces to assess GOI. We evaluate the effectiveness of the system by analysing different test samples with varying defect density. From the GOI results, we calculate the key parameter for GOI measurement, such as defect density across different wafers. Additional key findings include determining the optimal gate size of the sample for accurate GOI measurement and identifying the local variation of defects across the wafer. Moreover, through in-depth data analysis, we observe that the GOI measurement data accurately correlates with the sample specification provided by the manufacturer. Overall, this GOI measurement system shows potential to benefit both aca-demic research and industry applications.Description
Supervisor
Savin, HeleThesis advisor
Setälä, OlliKeywords
gate oxide integrity, Fowler-Nordheim tunneling, voltage ramp stress test, time zero dielectric breakdown, defect density