Procedural Design, Verification and Implementation Framework for Analog Amplifiers
Loading...
Access rights
openAccess
URL
Journal Title
Journal ISSN
Volume Title
A4 Artikkeli konferenssijulkaisussa
This publication is imported from Aalto University research portal.
View publication in the Research portal (opens in new window)
View/Open full text file from the Research portal (opens in new window)
View publication in the Research portal (opens in new window)
View/Open full text file from the Research portal (opens in new window)
Authors
Lahtinen, Veeti
Porrasmaa, Santeri
Kosunen, Marko
Ryynänen, Jussi
Date
2024-06-03
Major/Subject
Mcode
Degree programme
Language
en
Pages
4
Series
Abstract
This paper presents a modular, parasitic-aware, process agnostic design and verification procedure. The procedure utilizes TheSyDeKick simulation and verification framework in combination with Berkeley Analog Generator (BAG). BAG is utilized to programmatically construct the schematic and layout in order to provide the parasitic component information for the algorithmic optimization procedure. This enables the most accurate definition of transistor sizing parameters to obtain the desired linearity, speed and noise performance. As the generation, extraction and design procedures are fully automated, this remarkably speeds up the design exploration. The presented procedural optimization is extensible to wide range of analog building blocks, and the effectiveness of method is demonstrated in context of a single-stage operational transconductance amplifier (OTA). The proposed method incorporates an algorithm that automatically sizes the design to achieve minimal current consumption for a given speed specification and provides a manufacturing-ready circuit implementation. The algorithm is demonstrated to effectively converge on final designs for various speed specifications with two distinct semiconductor processes.Description
Keywords
algorithmic design, analog design, design automation, TheSyDeKick, Berkeley Analog Generator
Other note
Citation
Lahtinen, V, Porrasmaa, S, Kosunen, M & Ryynänen, J 2024, Procedural Design, Verification and Implementation Framework for Analog Amplifiers . in 2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) . IEEE, Volos, Greece, pp. 1-4, International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design, Volos, Greece, 02/07/2024 . https://doi.org/10.1109/SMACD61181.2024.10745440