Embedded technologies have experienced rapid growth over the past few decades. As an essential part of embedded devices, the rapid advancement of the embedded systems has led to an increasing demand for efficient memory solutions, particularly in resource-constrained environments where balancing performance, cost and capacity is critical. Currently, both industry and academia are coming up with innovative memory solutions.
The processor project called 'A-Core', which began in 2020 and has steadily continued with new extensions and improvements over the years of development at Aalto University, faces the challenge of the memory capacity limitations. Due to the high cost of on-chip memory scaling and the precious chip area, an off-chip memory solution with controller had to be used. Among the numerous off-chip memory interfaces and technologies, the HyperBus protocol is the optimal choice due to its low pin counts, excellent performance, and simplified controller design. For example, the pin count of the HyperRAM is at a minimum of 11 for the bus signals, while other technologies use three times more pins and still achieve similar data throughput.
Moreover, the commercial solutions for the HyperBus memory solutions usually have specific IP cores that do not meet the requirements of the 'A-Core' project, so the team at Aalto University decided to develop their own HyperBus memory controller. Based on this background, the goal of the thesis is to further optimise the HyperBus memory controller which has been developed in the project 'A-Core' for the specific FPGA development board, so that the design could complie with the requirements for running on FPGA develop board. In addition, the work also includes the implementation of the controller in the integrated development environment (IDE), which indicates the feasibility of running the design on FPGAs.
The design and its implementation of the HyperBus memory controller for the sepcific FPGA platform based on the HyperBus protocol has been successfully completed. The basic read/write function is verified by simulations. And the timing, power and utilization reports show that it could work at the target frequency at the FPGA board. Although the hardware verification is not completed, the thesis work provides an important reference for the further debugging.
